Printed circuit board using paste bump and manufacturing method thereof

ABSTRACT

A printed circuit board using paste bumps and manufacturing method thereof are disclosed. With the method of manufacturing a printed circuit board using paste bumps, comprising: (a) perforating a core board to form at least one via hole, (b) filling the at least one via hole by fill-plating and forming a circuit pattern on at least one surface of the core board, (c) stacking a paste bump board on at least one surface of the core board, and (d) forming an outer layer circuit on a surface of the paste bump board, a structurally stable all-layer IVH structure can be implemented due to increased strength in the BVH&#39;s of the plated core boards, the manufacture time can be reduced due to parallel processes and collective stacking, implementing micro circuits can be made easy due to the copper foils of the paste bump boards stacked on the outermost layers, the manufacture costs can be reduced as certain plating and drilling processes may be omitted, the interlayer connection area is increased between circuit patterns for improved connection reliability, and dimple coverage can be obtained.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No.2005-0109850, filed with the Korean Intellectual Property Office on Nov.16, 2005, and Korean Patent Application No. 2005-0109855 filed on Nov.16, 2005, the disclosures of which are incorporated herein by referencein their entirety.

BACKGROUND

1. Technical Field

The present invention relates to a printed circuit board, and inparticular, to a printed circuit board using paste bumps and amanufacturing method thereof.

2. Description of the Related Art

The conventional multilayer printed circuit board is manufactured byforming inner layer circuits on the surface of a core board, such as acopper clad laminate (CCL), etc., through the application of an additiveprocess or a subtractive process, etc., and by forming outer layercircuits through the stacking of insulation layers and metal layers inorder, by the same method as for the inner layer circuits.

During the manufacturing process of a multilayer printed circuit board,various via holes are formed, such as IVH's (interstitial via holes),BVH's (blind via holes), and PTH's (plated through holes), etc., forelectrical connection between the circuit patterns of each layer andbetween a circuit pattern and an electronic element. Among these, thePTH's, which are formed penetrating the entire thickness in the crosssection of a board, also function as heat-releasing holes, in additionto the function of electrical connection mentioned above.

With developments in electronic components, there is a demand fortechnology which can improve the performance of HDI (high densityinterconnection) boards, to which the concepts of interlayer electricalconnection and micro circuit wiring have been applied for higher densityprinted circuit boards. That is, to improve the performance of HDIboards, a technology is required which provides interlayer electricalconnection and an adequate degree of freedom.

The method of manufacturing a multilayer printed circuit board accordingto prior art includes first perforating via holes (e.g. IVR's, etc.) ina core board (e.g. a CCL, etc.) by mechanical drilling, etc., formingplating layers (e.g. by chemical copper plating and/or copperelectroplating, etc.) on the surfaces of the core board and on the innerperimeters of the via holes, filling the inside spaces of the IVH's andpolishing the surfaces, and then forming inner layer circuits on thesurfaces of the core board by applying an additive or a subtractiveprocess, etc., and inspecting the circuits. Next, a build-up process isperformed by procedures of surface treatment and stacking RCC (resincoated copper), etc., and via holes are formed for interlayer electricalconnection between circuit patterns by laser drilling, etc., after whichouter layer circuits are formed on the surface of the stacked board andthe circuits are inspected. To add more layers of circuit patterns, theprocess is repeated of surface treatment and stacking RCC, etc., formingvia holes, plating the surfaces of the via holes, and afterwards formingouter layer circuits. Such a build-up process is repeated to form adesired number of circuit pattern layers.

That is, metal layers are formed after stacking insulation material, orinsulation material that has a metal layer formed on its surface (e.g.RCC, etc.) is stacked, on the surfaces of a core board, after whichBVH's are processed by laser drilling, etc., for electrical connectionbetween metal layers and inner layer circuits, PTH's which penetrate theentire cross section of the printed circuit board are perforated bymechanical drilling, etc., outer layer circuit layers are formed on thesurfaces of the insulation material by the same method as for the innerlayer circuits, and the inner perimeters of the PTH's are plated so thatthe PTH's function as heat-releasing holes.

However, the conventional manufacturing process for multilayer printedcircuit boards is unable to comply to requests for low costs accordingto lowering prices in the applied products (e.g. cell phones, etc.) andrequests for reduced lead times for increased productivity, and thusthere is a demand for a new manufacturing process that can resolve suchproblems.

Also, the conventional method requires a plating process which iscomplicated, expensive, and time-consuming, and does not provide asufficient heat-releasing effect through the PTH's. Also, when formingcircuit patterns after forming the plating layer, the conventionalmethod presents difficulties in forming micro circuits, caused by theincrease in thickness of the circuit patterns due to the plating layer.

Meanwhile, in order to simplify the complicated process of prior art andto manufacture a multilayer printed circuit quickly and inexpensively bya collective stacking procedure, the so-called “B2IT (buried bumpinterconnection technology)” has been commercialized, which allows asimple and convenient stacking process by printing paste on a copperfoil 3 to form bumps 2′ and stacking an insulation material 1 thereon toprefabricate a paste bump board, as illustrated in FIG. 1.

Prior art related to the paste bump board includes an invention whichuses a paste bump board having bumps made of conductive paste formed ona copper foil to allow simple and easy interconnection between theterminals of high-density electronic components. This invention,however, implements all-layer IVH's with only the paste bump board sothat it has a weak structure. Also, there is a likelihood of shortcircuits occurring in a high-voltage, high-frequency environment, andthere are paste bumps filled in the board's via holes so that theproperties of heat release through PTH's have not been improved.

SUMMARY

The present invention aims to provide a printed circuit board and amanufacturing method thereof, with which a multilayer printed circuitboard is formed by collectively stacking a core board having platedBVH's, a board having paste bumps printed on a core board, and a pastebump board, to implement a structurally stable all-layer IVH structure,improve the connection reliability by means of an increase in interlayerconnection area, and reduce lead times. Another object of the presentinvention is to provide a printed circuit board using paste bumps and amanufacturing method thereof, for which paste bump boards are stacked ona core board and paste bumps are filled in heat-releasing holes, suchthat the heat-releasing effect is improved.

One aspect of the present invention provides a method of manufacturing aprinted circuit board using paste bumps, comprising: (a) perforating acore board to form at least one via hole, (b) filling the at least onevia hole by fill-plating and forming a circuit pattern on at least onesurface of the core board, (c) stacking a paste bump board on at leastone surface of the core board, and (d) forming an outer layer circuit ona surface of the paste bump board.

It may be preferable that the core board be a copper clad laminate(CCL), which has a copper foil layer stacked on its surface. In certainembodiments, the method may further include an operation of removing thecopper foil layer in correspondence with a position where the at leastone via hole is to be formed, before the operation (a) of perforating acore board to form at least one via hole. The method may also-furtherinclude an operation of reducing the thickness of the copper foil layerby half-etching, between the operation (a) of perforating a core boardto form at least one via hole and the operation (b) of filling the atleast one via hole by fill-plating and forming a circuit pattern on atleast one surface of the core board. The via hole may preferably be ablind via hole (BVH).

Preferably, the paste bump board may be formed by (e) printing at leastone paste bump on a copper foil, (f) setting the at least one pastebump, and (g) stacking an insulation material on the copper foil suchthat the at least one paste bump penetrates the insulation material.

A plating layer, formed by the fill-plating in the at least one viahole, may preferably comprise a dimple, with the at least one paste bumpformed in correspondence with a position of the dimple. The strength ofthe paste bump may preferably be lower than that of the plating layerand greater than that of the insulation material. The paste bump mayinclude silver paste.

In certain embodiments, the method may further include an operation ofpressing the paste bump board onto the core board, between the operation(c) of stacking a paste bump board on at least one surface of the coreboard and the operation (d) of forming an outer layer circuit on asurface of the paste bump board.

Another aspect of the invention provides a method of manufacturing aprinted circuit board using paste bumps by collectively stacking atleast one first core board, at least one second core board, and at leastone outer layer board, in which the first core board is formed by (a)forming at least one BVH (blind via hole) on one surface of a coremember, and (b) filling the at least one BVH by fill-plating and forminga circuit pattern on at least one surface of the core member; the secondcore board is formed by (c) joining at least one core bump onto theother surface of the core member of the first core board in a positionwhere the at least one BVH is formed, (d) setting the at least one corebump, and (e) stacking a core insulation material on the other surfaceof the core member such that the at least one core bump penetrates thecore insulation material; while the outer layer board is formed by (f)joining at least one outer layer bump onto a copper foil, (g) settingthe at least one outer layer bump, and (h) stacking an outer layerinsulation material on the copper foil such that the at least one outerlayer bump penetrates the outer layer insulation material.

The core member may preferably be a copper clad laminate (CCL), whichhas a copper foil layer stacked on its surface. In certain embodiments,the method may further include an operation of removing the copper foillayer in correspondence with a position where the BVH is to be formed,before the operation (a) of forming at least one BVH on one surface of acore member. The method may also further include an operation ofreducing the thickness of the copper foil layer by half-etching, betweenthe operation (a) of forming at least one BVH on one surface of a coremember and the operation (b) of filling the at least one BVH byfill-plating and forming a circuit pattern on at least one surface ofthe core member.

The at least one core bump or the at least one outer layer bump may beformed by printing silver paste. It may be preferable for a platinglayer, formed by the fill-plating in the at least one BVH, to comprise adimple, while the at least one core bump or the at least one outer layerbump may be formed in correspondence with a position of the dimple.

The printed circuit board may be formed by aligning and stacking aplurality of the first core boards or a plurality of the second coreboards such that the at least one core bump or the at least one outerlayer bump is in correspondence with a position of the dimple, andafterwards pressing the at least one outer layer board.

Still another aspect of the invention provides a printed circuit boardusing paste bumps, comprising: a core board, a BVH (blind via hole)formed in the core board, a plating layer filled in the BVH, a circuitpattern formed on at least one surface of the core board, a dimpleincluded in the plating layer, and a paste bump board stacked on thecore board, in which the paste bump board is formed by joining at leastone paste bump onto a copper foil and stacking an insulation material onthe copper foil such that the at least one paste bump penetrates theinsulation material. The core board may preferably be a copper cladlaminate (CCL), which has a copper foil layer stacked on its surface. Itmay be preferable that the at least one paste bump be joined incorrespondence with a position of the dimple. It may also be preferablethat the at least one paste bump be filled in the dimple and beelectrically connected with the plating layer. It may also be preferablethat the paste bump have a strength lower than that of the plating layerand greater than that of the insulation material. The printed circuitboard may further comprise an outer layer circuit formed by removingportions of the copper foil.

Meanwhile, the printed circuit board may further comprise an extra boardpositioned between the core board and the paste bump board, while theextra board may comprise an extra BVH (blind via hole) formed on onesurface of the extra board, an extra plating layer filled in the extraBVH, an extra circuit pattern formed on at least one surface of theextra board, an extra dimple included in the extra plating layer, and anextra bump joined to the other side of the extra board in a positionwhere the extra BVH is formed, where it may be preferable that the extrabump be filled in the dimple and be electrically connected with theplating layer, and that the paste bump be filled in the extra dimple andbe electrically connected with the extra plating layer.

The paste bump, the extra plating layer, and the plating layer may forman all-layer IVH (interstitial via hole).

Yet another aspect of the invention provides a method of manufacturing aprinted circuit board using paste bumps, comprising: (a) perforating acore board to form at least one via hole, (b) forming an inner layercircuit on at least one surface of the core board, (c) stacking a pastebump board on at least one surface of the core board, and (d) forming anouter layer circuit on a surface of the paste bump board.

The core board may preferably be a copper clad laminate (CCL), and theoperation (a) of perforating a core board to form at least one via holemay preferably comprise perforating the at least one via hole bymechanical drilling. The operation (a) of perforating a core board toform at least one via hole further may further comprise forming aplating layer on an inner perimeter of the at least one via hole.

It may be preferable for the paste bump board to be formed by (e)printing at least one paste bump on a copper foil in correspondence witha position where the at least one via hole is formed, and (f) settingthe at least one paste bump. The method may further comprise anoperation of stacking an insulation material on the copper foil suchthat the at least one paste bump penetrates the insulation material,after the operation (f) of setting the at least one paste bump.

The at least one paste bump may include silver paste. It may bepreferable that the amount of the at least one paste bump be determinedin correspondence with a size of the at least one via hole such that theat least one via hole is filled. Preferably, the paste bump may have astrength lower than that of the plating layer and greater than that ofthe insulation material. It may be preferable that the paste bump beformed in a shape of a BVH (blind via hole) which electrically connectsthe inner layer circuit and the outer layer circuit.

The operation (c) of stacking a paste bump board on at least one surfaceof the core board may include an operation of stacking the paste bumpboard on both surfaces of the core board. Also, an operation of pressingthe paste bump board on both surfaces of the core board may further beincluded between the operation (c) of stacking a paste bump board on atleast one surface of the core board and the operation (d) of forming anouter layer circuit on a surface of the paste bump board.

Still another aspect of the invention provides a printed circuit boardusing paste bumps, comprising: a core board, a via hole formed byperforating a portion of the core board, an inner layer circuit formedon at least one surface of the core board, a paste bump board formed byjoining at least one paste bump on a copper foil layer and stacking aninsulation material and stacked on a surface of the core board, and anouter layer circuit formed on a surface of the paste bump board, inwhich the at least one paste bump is joined in correspondence with aposition of the via hole, and the via hole is filled by the at least onepaste bump.

The core board may preferably be a copper clad laminate (CCL). A platinglayer may be formed on an inner perimeter of the via hole. It may bepreferable that the plating layer have varying thickness along its depthfrom the opening of the via hole, such that the via hole is formed in ashape corresponding with a shape of the at least one paste bump. Also,it may be preferable for the thickness of the plating layer to increasealong its depth from the opening of the via hole.

The paste bump board may preferably be formed by printing at least onepaste bump on a copper foil, setting the at least one paste bump, andafterwards stacking an insulation material on the copper foil such thatthe at least one paste bump penetrates the insulation material.

The paste bump may include silver paste. Preferably, the amount of thepaste bump may be determined in correspondence with the size of the viahole. It may also be preferable that the paste bump have a strengthlower than that of the plating layer and greater than that of theinsulation material.

It may be preferable that the paste bump be formed in the shape of a BVH(blind via hole) which electrically connects the inner layer circuit andthe outer layer circuit. It may also be preferable that the paste bumpboard be stacked on both surfaces of the core board.

Additional aspects and advantages of the present invention will be setforth in part in the description which follows, and in part will beobvious from the description, or may be learned by practice of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a paste bump board according toprior art.

FIG. 2 is a flowchart illustrating a method of manufacturing a printedcircuit board using paste bumps according to an embodiment of thepresent invention.

FIG. 3 is a flowchart illustrating a method of manufacturing a printedcircuit board using paste bumps according to another embodiment of thepresent invention.

FIG. 4 is a flow diagram illustrating a process of manufacturing aprinted circuit board using paste bumps according to an embodiment ofthe present invention.

FIG. 5 is a cross-sectional view of a printed circuit board using pastebumps according to an embodiment of the present invention.

FIG. 6 shows cross-sectional views comparing the respective structuralstability of a printed circuit board using paste bumps according to anembodiment of the present invention and a printed circuit board usingpaste bumps according to prior art.

FIG. 7 shows photographs illustrating all-layer IVH structures of aprinted circuit board using paste bumps according to an embodiment ofthe present invention.

FIG. 8 shows photographs illustrating all-layer IVH structures of aprinted circuit board using paste bumps according to another embodimentof the present invention.

FIG. 9 shows photographs illustrating dimple coverage in a printedcircuit board using paste bumps according to an embodiment of thepresent invention.

FIG. 10 is a flowchart illustrating a method of manufacturing a printedcircuit board using paste bumps according to another embodiment of thepresent invention.

FIG. 11 is a flow diagram illustrating a process of manufacturing aprinted circuit board using paste bumps according to another embodimentof the present invention.

FIG. 12 is a cross-sectional view of a printed circuit board using pastebumps according to another embodiment of the present invention.

FIG. 13 is a cross-sectional view of a printed circuit board using pastebumps according to another embodiment of the present invention.

DETAILED DESCRIPTION

Embodiments of the printed circuit board using paste bumps andmanufacturing method thereof, according to aspects of the invention,will be described below in more detail with reference to theaccompanying drawings. In the description with reference to theaccompanying drawings, those components are rendered the same referencenumber that are the same or are in correspondence regardless of thefigure number, and redundant explanations are omitted.

FIG. 2 is a flowchart illustrating a method of manufacturing a printedcircuit board using paste bumps according to an embodiment of thepresent invention.

The present invention is for reducing the manufacture costs and times ofa multilayer printed circuit board by collectively stacking paste bumpboards on a core board, where a paste bump board is formed by performingplating on BVH's (blind via holes) formed in a core board, printingpaste bumps on a copper foil in correspondence with the positions of theBVH's, and then stacking an insulation material. To this end, first, viaholes are formed by perforating the core board (100).

For the core board, it is generally efficient to use a copper cladlaminate (CCL), which has a copper foil layer stacked on its surface, asit is effective in forming circuit patterns. Meanwhile, although thepresent embodiment is described using BVH's as an example, the via holesaccording to the present invention are not necessarily limited to BVH's.

When a copper clad laminate is used for the core board, it isadvantageous to remove the copper foil layer in the correspondingportions (90) and form window portions for forming BVH's, beforeremoving portions of the core board to form BVH's.

Next, the surface of each of the BVH's is fill-plated to form a platinglayer, and a circuit pattern is formed on the surface of the core board(110). When fill-plating is performed on a typical BVH, the plating doesnot result in a flat surface, but rather forms a particular concave,i.e. a dimple is formed. However, the present invention is notnecessarily limited to cases in which a dimple is formed in the platinglayer, and it is apparent to those skilled in the art that the inventioncan be applied to cases in which the surface is made flat by theplating, without the forming of a dimple.

Since, during the plating of the BVH's, the plating layer is formed alsoon the surface of the core board, the thickness of the copper foil layerformed on the surface of the core board is increased, which presentsdifficulties in forming minute circuit patterns on the surface of thecore board. Therefore, by reducing the thickness of the copper foillayer on the surface of the core board to a certain level by means ofhalf-etching (105), before performing the plating in the BVH's, thethickness of the plating layer on the core board surface need not beincreased, and a circuit pattern may be formed in a required degree ofprecision.

Next, paste bump boards are stacked on the surfaces of the core board(120). A paste bump board is formed by printing paste bumps on thesurface of a copper foil (122) and setting the printed paste bumps(124).

By thus manufacturing the paste bump boards separately and collectivelystacking onto the core board, the manufacturing process for the printedcircuit board may be reduced. To make the collective stacking processmore efficient, insulation material is stacked onto the copper foil onwhich paste bumps are formed (126).

As stacking the paste bump boards on the core board is to allow thepaste bumps to be electrically connected with the plating layer formedin the BVH's, it is advantageous for the thickness of the insulationmaterial stacked on the copper foil to be less than the height of thepaste bumps, so that the ends of the paste bumps are exposed through thesurface of the insulation material.

The paste bumps, printed on the copper foil and set, desirably has astrength lower than that of the plating layer on the core board andgreater than that of the insulation material. Thus, when the insulationmaterial is stacked on the copper foil, the paste bumps are not deformedbut instead penetrate the insulation material to be exposed through thesurface of the insulation material.

Also, in order to prevent the damaging of the plating layer by the pastebumps during the process of stacking and pressing the paste bump boardsonto the core board to electrically connect the paste bumps and theplating layer, it is desirable that the strength of the paste bumps belower than that of the plating layer on the core board.

In the process of stacking the paste bump boards on the core board, whenthe positions of the paste bumps are aligned with the positions of theBVH's, and the paste bump boards are pressed onto the core board (125),the paste bumps are deformed into the shape of the dimples in theplating layer mentioned above, to fill in the dimples. Thus, the pastebumps and the plating layer of the core board are attached and areelectrically connected.

While silver paste is typically used as the material for the pastebumps, other types of paste may obviously be used, within a scopeapparent to those skilled in the art, in consideration of the strength,cost, and applicability, etc., of the paste.

Lastly, outer layer circuits are formed on the surfaces of the pastebump boards (130) to complete the multilayer printed circuit board. Thesurface of a paste bump board, on which an outer layer circuit isformed, corresponds to the copper foil described above. Since suchprocesses as BVH drilling and plating, etc., for forming outer layercircuits are not required, the problem in prior art of increasedthickness of the copper foil layer caused by stacking RCC, etc., andplating may be avoided, whereby micro circuit patterns may readily beformed in implementing outer layer circuits.

FIG. 3 is a flowchart illustrating a method of manufacturing a printedcircuit board using paste bumps according to another embodiment of thepresent invention.

The method of manufacturing a multilayer printed circuit board accordingto the present invention is not limited to stacking paste bump boards ona single core board, but includes the case of collectively stacking aplurality of core boards and paste bump boards. The description belowwill illustrate as an example the case of manufacturing a multilayerprinted circuit board by collectively stacking two core boards and pastebump boards, which are the outer layer boards.

That is, in manufacturing a printed circuit board by collectivelystacking a first core board, a second core board, and paste bump boards,which are the outer layer boards (200), first, the first core board isformed (210) by forming BVH's on one surface of the core member (214),and filling the BVH's by fill-plating and forming a circuit pattern onthe surface of the core board (218).

As described earlier, it is desirable to use a copper clad laminate(CCL) for the core member, in which case it is desirable to remove theportions of the copper foil layer where the BVH's are to be formed (212)to create window portions before forming the BVH's. Also, before formingthe BVH's and plating, the thickness of the copper foil layer may bereduced by half-etching (216), to enable the implementation of microcircuits.

Next, the second core board is formed (220), which is for collectivelystacking with the first core board to form the multilayer printedcircuit board, by joining paste bumps to a board in the same form as thefirst core board.

That is, the second core board is formed by joining core bumps, incorrespondence with the positions on the first core board where theBVH's are formed, on the surface of the core member opposite the surfaceon which BVH's are formed (222) and by setting the core bumps (224). Itis efficient in terms of manufacture to form the core bumps in the samemanner as for the paste bumps described earlier. It is apparent,however, that the present invention is not necessarily limited to thecase in which the core bumps and the paste bumps are the same.

After joining the core bumps, a core insulation material is stacked onthe other surface of the core member such that the core bumps penetratethe insulation material (226), as for the case of the paste bump boarddescribed earlier, to complete the second core board. By thus stackingbeforehand the insulation material that is to be filled between thefirst and second core boards, a speedy manufacture by collectivestacking may be achieved.

Lastly, the outer layer boards are formed (230), which have the sameform as the paste bump boards described earlier. An outer layer board isformed by joining outer layer bumps on a copper foil (232), setting theouter layer bumps (234), and stacking an outer layer insulation materialonto the copper foil such that the outer layer bumps penetrate theinsulation material (236). Detailed descriptions on the outer layerboards will not be provided.

In the process of stacking the second core board on the first coreboard, the core bumps are filled in the dimples of the BVH's formed inthe first core board, by which the core bumps and the plating layerfilled in the BVH's of the first core board are electrically connected.

Since the core bumps are joined on the second core board in positionswhere the BVH's are formed, when the first core board, second coreboard, and outer layer boards are stacked in order, the plating layer ofthe first core board are electrically connected with the core bumps, thecore bumps are connected to the plating layer filled in the BVH's of thesecond core board, and the plating layer filled in the BVH's of thesecond core board is electrically connected with the outer layer bumps.

In other words, the plating layers filled in the BVH's of the first coreboard and second core board are electrically connected by the core bumpsand outer layer bumps to form IVH's (interstitial via holes). Such anall-layer IVH structure formed according to the present embodimentprovides a structure that is generally more stable, compared to thatformed by the stacking of conventional paste bump boards, since theintermediate core boards and plating layers provide sufficientstructural strength.

In order for the paste bumps to be filled in the dimples of the platinglayer and be electrically connected, the printed circuit board accordingto an embodiment of the invention is formed by stacking the first coreboard and second core board such that the core bumps are aligned in thepositions of the dimples, and then pressing the outer layer boards,which are paste bump boards. It is apparent that the number of coreboards may vary according to the number of circuit pattern layersrequired.

FIG. 4 is a flow diagram illustrating a process of manufacturing aprinted circuit board using paste bumps according to an embodiment ofthe present invention. In FIG. 4 are illustrated core members 10, 40,copper foil layers 12, window portions 14, BVH's 16, plating layers 18,dimples 19, 42, circuit patterns 20, 41, copper foils 30, paste bumps32, 44, insulation material 34, 46, and outer layer circuits 36.

As illustrated in FIG. 4, the multilayer printed circuit board accordingto the present embodiment is formed by concurrently manufacturing thefirst core board, second core boards, and paste bump boards, and thencollectively stacking afterwards. The descriptions are provided for eachunit process.

(1) Manufacturing Process for the First Core Board

To manufacture a first core board, which does not have paste bumps, acore member 10, such as a copper clad laminate (CCL), etc., is preparedas in (a1) of FIG. 4, to which pre-processing procedures such as baking,etc., have been applied. Then, as in (a2) of FIG. 4, the portions of thecopper foil layer 12 where the BVH's 16 are to be formed are removed toform window portions 14.

However, it is not necessary that the invention include a process offorming window portions 14, and as will be described later, while usingCO₂ laser to process BVH's 16 requires removing portions of the copperfoil layer 12 to form window portions 14, using YAG laser to processBVH's 16 does not require forming separate window portions 14, since itis able to process the copper foil layer 12 as well. As such, it is tobe appreciated that various BVH forming processes may be applied, withina scope apparent to those skilled in the art.

As in (a3) of FIG. 4, the BVH's are processed by means of mechanicaldrilling or laser (CO₂ or YAG laser) drilling. Before plating in theBVH's 16, the thickness of the copper foil layer 12 is reduced byhalf-etching, as in (a4) of FIG. 4. This is to prevent difficulties inimplementing micro circuits caused by an increase in the thickness ofthe copper foil layer 12 due to the plating.

As in (a5) of FIG. 4, the BVH's 16 formed on the core member 10 arefill-plated to form a plating layer 18. The fill-plating applied in theBVH's 16 is a process for rendering conductivity to the holes processedin the core member 10, which is of an insulating material. With typicalfill-plating, the BVH's 16 are not completely filled, but instead, theplating layer 18 is formed in accordance with the shape of the BVH's 16,to form dimples 19 having the shape of concave grooves in the openingportions of the BVH's 16.

In prior art, the dimples 19 formed when fill-plating was applied toBVH's 16 acted as obstacles to the electrical connection between theplating layer 18 and other circuit pattern layers. In embodiments of thepresent invention, the dimples 19 created by fill-plating are filled inwith the paste bumps 32 to improve the reliability of electricalconnection, whereby an effect of ‘dimple coverage’ may be obtained.

As in (a6) of FIG. 4, a circuit pattern forming process, includingexposing, developing, etching, and inspecting, is applied to the copperfoil layer 12 on the surface of the core member 10 to form circuitpatterns 20. With the completion of the circuit pattern forming process,the resulting board is transported for a lay-up process, which will bedescribed later.

(2) Manufacturing Process for the Paste Bump Board

On a copper foil 30, prepared as in (b1) of FIG. 4, conductive pastesuch as silver paste, etc., is printed as in (b2) of FIG. 4, to formpaste bumps 32. To enhance the efficiency of the collective stacking, aninsulation material 34 such as prepreg, etc., is stacked on the copperfoil 30 as in (b3) of FIG. 4. During this process, the paste bumps 32formed on the copper foil 30 penetrate the prepreg to be exposed throughthe surface of the insulation material 34.

By thus having the paste bumps 32 exposed through the surface of theinsulation material 34, the dimples 19 are filled by the paste bumps 32during the collective stacking. When the process of stacking theinsulation material 34 is completed, the resulting board is transportedfor a lay-up process, which will be described later.

(3) Manufacturing Process for the Second Core Board

As in (c1) of FIG. 4, the core board manufactured by the manufacturingprocess for the first core board is prepared, and as in (c2) of FIG. 4,paste bumps 44 are printed using conductive paste on the surfaceopposite the dimples 42 of the portions where the plating layer 18 ofthe BVH's 16 is formed. The paste bumps 44 joined to the second coreboard are electrically connected with the dimples of another core boardor with circuit patterns, while the dimples 42 of the plating layerformed on the second core board are filled by paste bumps joined toanother core board or to a paste bump board.

As in the case of a paste bump board, an insulation material 46 such asprepreg, etc., is stacked on the second core board, as in (c3) of FIG.4. During this process, the paste bumps 44 penetrate the prepreg toprotrude out to the surface of the insulation material 46.

By thus having the paste bumps 44 exposed through the surface of theinsulation material 46, the dimples 42 are filled by the paste bumps 44during the collective stacking. When the process of stacking theinsulation material 46 is completed, the resulting board is transportedfor a lay-up process, which will be described later.

(4) Lay-Up and Collective Stacking Process

As in (d) of FIG. 4, a lay-up process is performed for the first coreboard, second core boards, and paste bump boards, such that thepositions of the paste bumps are aligned with the positions of thedimples 19 of the plating layer 18, and the boards collectively stackedas in (e) of FIG. 4 are pressed together to manufacture the multilayerprinted circuit board. A conventional build-up process of prior art maybe applied to the ensuing process of forming outer layer circuits 36 onthe printed circuit board.

As illustrated in (d) and (e) of FIG. 4, several first core boards orsecond core boards may be stacked to obtain a required number of circuitpattern layers.

FIG. 5 is a cross-sectional view of a printed circuit board using pastebumps according to an embodiment of the present invention. In FIG. 5 areillustrated core members 10, plating layers 18, dimples 19, circuitpatterns 20, paste bumps 32, insulation materials 34, and outer layercircuits 36.

In the multilayer printed circuit board according to an embodiment ofthe invention, BVH's are formed in the core board and a plating layer 18is filled inside, and paste bump boards are stacked collectively to fillthe dimples 19 formed in the plating layers 18 with the paste bumps 32and implement electrical connections with the plating layers 18,consequently forming an all-layer IVH structure composed of platinglayers 18 and paste bumps 32.

That is, the multilayer printed circuit board according to an embodimentof the invention comprises a core board such as a copper clad laminate,etc., BVH's formed in the core board, plating layers 18 filled in theBVR's, and paste bump boards stacked on the core board, where a pastebump board is formed by printing and setting paste bumps 32 on a copperfoil 30, and then stacking an insulation material 34 so that the pastebumps 32 penetrate the insulation material 34.

As described earlier, dimples 19 are formed in the plating layer 18filled in the BVH's by typical fill-plating, and such dimples 19 act asobstacles to the interlayer electrical connection between circuitpatterns 20. In embodiments of the present invention, however, pastebump boards having paste bumps 32 formed corresponding with thepositions of the dimples 19 are stacked on the core board, so that thepaste bumps 32 fill the dimples 19, and become electrically connectedwith the plating layer 18.

In stacking the insulation material 34 on the paste bump board, thestrength of the paste bumps 32 must be greater than that of theinsulation material 34 to allow the paste bumps 32 to penetrate theinsulation material 34, while the strength of the paste bumps 32 must belower than that of the plating layer 18 for the paste bumps 32 to fillthe dimples 19 and form an electrical connection with the plating layer18. Here, during the process of pressing and stacking the paste bumpboards onto the core boards, the paste bumps 32 are deformed in shapeaccording to the shape of the dimples 19, and the paste bumps 32 arefilled in the dimples 19.

After the completion of the collective stacking, a typical circuitpattern forming process is applied on the copper foils 30, i.e. theoutermost layers, of the multilayer printed circuit board to form outerlayer circuits 36.

Meanwhile, embodiments of the present invention include a multilayerprinted circuit board, in which one or more additional core boards arefurther included between the core board and the paste bump boards toprovide a desired number of circuit pattern layers. In this case, theadditional core boards (hereafter referred to as “extra boards”), aswith the core board described earlier, each have BVH's formed on onesurface with a plating layer 18 filled in the BVH's, and have pastebumps 32 joined on the surface opposite the dimples 19 of the platinglayer 18 in the positions where the BVH's are formed.

In stacking the extra boards thus formed on the core board, the pastebumps joined onto the extra boards fill the dimples 19 of the core boardand become electrically connected with the plating layer 18. By stackinganother extra board or a paste bump board on the extra board, thedimples 19 formed in the plating layer 18 of the extra board is filledwith paste bumps 32 to be electrically connected with the plating layer18 of the extra board.

That is, when one or more extra boards are placed between the core boardand the paste bump boards, the plating layer 18 and paste bumps 32 ofeach board are connected to generally form all-layer IVH's. Since suchIVH's have plating layers 18 arranged intermediately, they arestructurally more stable, compared to all-layer IVH's formed by stackingonly paste bump boards.

FIG. 6 shows cross-sectional views comparing the respective structuralstability of a printed circuit board using paste bumps according to anembodiment of the present invention and a printed circuit board usingpaste bumps according to prior art. In FIG. 6 are illustrated coreboards 10, a plating layer 18, copper foils 30, 31, and paste bumps 32,33.

As shown in (a) of FIG. 6, for an all-layer IVH formed by stacking onlypaste bump boards, the entire structure is formed only with copper foils31 and insulation material, and the insufficient strength in the innercore portions results in a structurally unstable composition. This maycause problems such as short circuits between the paste bumps 33 andcopper foils 31 when a high-voltage, high-frequency current flowsthrough the printed circuit board.

On the other hand, an all-layer IVH according to an embodiment of theinvention, as shown in (b) of FIG. 6, has a structurally stablecomposition, since the core boards 10 and the plating layers 18 from thefill-plating provide sufficient structural strength. The paste bumps 32fill the dimples to connect with the plating layer, and the copper foils30 provide thin copper foil layers which enable the forming of minuteouter layer circuits 36.

FIG. 7 shows photographs illustrating all-layer IVH structures of aprinted circuit board using paste bumps according to an embodiment ofthe present invention, FIG. 8 shows photographs illustrating all-layerIVH structures of a printed circuit board using paste bumps according toanother embodiment of the present invention, and FIG. 9 showsphotographs illustrating dimple coverage in a printed circuit boardusing paste bumps according to an embodiment of the present invention.In FIGS. 7 to 9 are illustrated plating layers 18 and paste bumps 32.

FIGS. 7 and 8 show stable all-layer IVH's, in which all of the layers inthe cross section are electrically connected, having plating layers 18on a plurality of core boards connected respectively by paste bumps 32,and paste bump boards stacked as the outer layers.

A dimple is formed, which is a concave portion formed due to the shapeof a BVH, in the plating layer 18 filled in each of the BVH's of thecore board, and when boards having paste bumps 32 are stackedcollectively as in the present embodiment, the paste bumps 32 aredeformed in accordance with the shape of the dimples to be electricallyconnected with the plating layer 18.

Since the paste bumps 32 are thus filled in the dimples and areelectrically connected with the plating layer 18, the reliability isimproved of interlayer electrical connection between circuit patterns20, and ‘dimple coverage’ is attained as a solution to the problem ofdifficulty in electrical connection caused by dimples.

FIG. 10 is a flowchart illustrating a method of manufacturing a printedcircuit board using paste bumps according to another embodiment of thepresent invention, and FIG. 11 is a flow diagram illustrating a processof manufacturing a printed circuit board using paste bumps according toanother embodiment of the present invention. In FIG. 11 are illustratedpaste bump boards 8 a, a core board 10 a, copper foil layers 12 a, viaholes 20 a, plating layers 22 a, inner layer circuits 30 a, copper foils40 a, outer layer circuits 42 a, paste bumps 50 a, and insulationmaterial 60 a.

In order to improve the efficiency of heat release in a printed circuitboard using paste bump boards 8 a having paste bumps 50 a formedbeforehand on copper foils 40 a, in an embodiment of the presentinvention, a core board 10 a such as shown in (a1) of FIG. 11 hasportions thereof perforated as in (a2) of FIG. 11 to form via holes 20 a(P100).

For increased efficiency in forming inner layer circuits 30 a, it isadvantageous to use a copper clad laminate (CCL) for the core board 10a. As the via holes 20 a function not only as electrical connectionmeans between interlayer circuit patterns but also as heat-releasingholes for releasing heat generated in the board, their size isdetermined in consideration of heat-releasing efficiency, and since theyrequire a lower degree of precision than do IVH's or BVH's, they may beperforated using mechanical drilling.

Plating layers 22 a are formed as in (a3) of FIG. 11 on the innerperimeters of the via holes 20 a not only for interlayer electricalconnection between circuit patterns but also for better heat conduction,to improve the efficiency of heat release. As such, the thickness of theplating layers 22 a on the inner perimeters of via holes 20 a used asheat-releasing holes is greater than that for other via holes 20 a, inconsideration of both electrical connection and heat conduction.However, methods of manufacturing a printed circuit board according toembodiments of the invention do not necessarily require plating layers22 a on the inner perimeters of the via holes 20 a, and it is to beappreciated that other methods of electrical connection may be usedwithin a scope apparent to those skilled in the art, such as ofimplementing interlayer electrical connection between circuit patternsby means of paste bumps 50 a, etc, as will be described later.

During the process of plating the inner perimeters of the via holes 20a, plating layers 22 a are formed also on the surfaces of the core board10 a, whereby the thickness of the circuit patterns is increased, whichis unfavorable to implementing micro circuit patterns. In this case, theplating process may be omitted, as in an embodiment of the invention,with the inner layer circuits 30 a formed only from the copper foillayers 12 a on the surfaces of the core board 10 a, to more readilyimplement micro circuit patterns. When the plating layers 22 a are notformed on the inner perimeters of the via holes 20 a, the interlayerelectrical connection between circuit patterns is achieved by means ofconductive paste bumps 50 a filled in the via holes 20 a.

Next, inner layer circuits 30 a are formed on the surfaces of the coreboards 10 a (P110), as in (a4) of FIG. 11. A subtractive process may beapplied in forming the inner layer circuits 30 a, and when the platingprocess is omitted, as described earlier, more minute circuit patternsmay be implemented.

Next, paste bump boards 8 a are stacked onto surfaces of the core board10 a (P120), as shown in (c) of FIG. 11. A paste bump board 8 a is aboard in which paste bumps 50 a have been printed beforehand on thesurface of a copper foil 40 a. To manufacture a paste bump board 8 a, acopper foil 40 a such as that shown in (b1) of FIG. 11 has paste bumps50 a printed in correspondence with the positions of the via holes 20 aformed in the core board 10 a (P 122), as shown in (b2) of FIG. 11,after which the paste bumps 50 a are set (P124).

Manufacturing the paste bump boards 8 a separately and stacking themcollectively on a core board 10 a reduces the manufacturing process ofthe printed circuit board, and to render the collective stacking processeven more efficient, insulation material 60 a is stacked on the copperfoils 40 a having paste bumps 50 a (P 126), as in (b3) of FIG. 1.

As the paste bumps 50 a are filled in the via holes 20 a of the coreboard 10 a from stacking the paste bump boards 8 a on the core board 10a, as illustrated in (c) of FIG. 11, it is desirable that the thicknessof an insulation material 60 a stacked onto the copper foils 40 a beless than the height of the paste bumps 50 a so that the ends of thepaste bumps 50 a are exposed through the surface of the insulationmaterial 60 a.

It is advantageous for the paste bumps 50 a printed and set on a copperfoil 40 a to have a strength lower than that of the core board 10 a butgreater than that of the insulation material 60 a. Thus, when theinsulation material 60 a is stacked on the copper foil 40 a, the pastebumps 50 a penetrate the insulation material 60 a to be exposed throughthe surface of the insulation material 60 a without being deformed.

Also, to prevent damages on the core board 10 a from the paste bumps 50a during the process of stacking paste bump boards 8 a onto the coreboard 10 a and pressing such that the paste bumps 50 a fill in the viaholes 20 a, it is advantageous for the strength of the paste bumps 50 abe lower than the strength of the core board 10 a.

In this case, when the positions of the paste bumps 50 a are alignedwith the positions of the via holes 20 a and the paste bump boards 8 aare pressed onto the core board 10 a, the form of the paste bumps 50 ais deformed in accordance with the form of the via holes 20 a in thecore board 10 a, to be filled inside the via holes 20 a.

While silver paste is typically used as the material for the paste bumps50 a, it is to be appreciated that other types of paste may be used,within a scope apparent to those skilled in the art, in consideration ofthe strength, cost, and applicability of the paste.

Using conductive paste can further increase the efficiency of heatrelease through the via holes 20 a filled in with the paste bumps 50 a,and as described earlier, interlayer electrical connection may beimplemented by the via holes 20 a without forming plating layers 22 a onthe inner perimeters of the via holes 20 a.

The amount of a paste bump 50 a printed on a copper foil 40 a isdetermined in correspondence with the size of a via hole 20 a. This isto allow the paste bumps 50 a to fill the via holes 20 a formed in thecore board 10 a when stacking the paste bump board 8 a on the core board10 a.

Stacking the paste bump boards 8 a onto the surfaces of the core board10 a provides outer layer circuits 42 a that are insulated from innerlayer circuits 30 a formed on the surfaces of the core board 10 a, andsince the interlayer connection between such circuit patterns areobtained through BVH's (blind via holes), it is desirable that the pastebumps 50 a be formed to function as BVH's that electrically connect theinner layer circuits 30 a and outer layer circuits 42 a.

Here, the paste bumps 50 a do not necessarily have to be formed inpositions where there are via holes 20 a, but may be formed in positionswhere electrical connection with an inner layer circuit 30 a isrequired.

Next, as in (d) of FIG. 11, the paste bump boards 8 a are stacked onboth surfaces of the core board 10 a. Stacking the paste bump boards 8 ais achieved by aligning the paste bump boards 8 a with the core board 10a, as in (c) of FIG. 11, and then pressing the paste bump boards ontoboth surfaces of the core board 10 a (P130).

This allows the paste bumps 50 a to fill in the via holes 20 a such thatthe via holes 20 a can function as heat-releasing holes. As describedearlier, when plating layers 22 a are not formed on the inner perimetersof the via holes 20 a, the via holes 20 a also function as IVH's thatimplement interlayer connection between circuit patterns. Thus,embodiments of the invention may provide all-layer IVH's that span theentire cross section, whereby the interlayer connection paths betweencircuit patterns may be reduced, to the effect of decreased inductancenoise.

Lastly, as in (e) of FIG. 11, outer layer circuits 42 a are formed onthe copper foils 40 a, i.e. the surfaces of the paste bump boards 8 a(P140). As with the inner layer circuits 30 a, a typical additiveprocess or subtractive process may be applied to forming the outer layercircuits 42 a.

FIG. 12 is a cross-sectional view of a printed circuit board using pastebumps according to another embodiment of the present invention. In FIG.12 are illustrated are illustrated a core board 10 a, copper foil layers12 a, via holes 20 a, plating layers 22 a, inner layer circuits 30 a,copper foils 40 a, outer layer circuits 42 a, paste bumps 50 a, andinsulation materials 60 a.

The printed circuit board according to the present embodiment is formedby pressing paste bump boards on both sides of a core board 10 a, whichhas inner layer circuits 30 a formed on its surfaces and via holes 20 aperforated, where a paste bump board is formed by joining paste bumps 50a on a copper foil 40 a in correspondence with the positions of the viaholes 20 a and stacking an insulation material 60 a onto the paste bumps50 a such that the paste bumps 50 a penetrate the insulation material 60a to be exposed through the surface of the insulation material 60 a.

It is desirable to use a copper clad laminate (CCL) for the core board10 a, to increase efficiency in forming circuit patterns. Electricalconnection is implemented for the circuit patterns formed on bothsurfaces of the core board 10 a, by coating metal layers on the innerperimeters of typical via holes 20 a by plating. As described earlier,since the plating layers 22 a formed on the inner perimeters of the viaholes 20 a not only provide electrical connection but also transfer heatgenerated in the board to be released to the exterior, the coating has agreater thickness compared to typical plating thicknesses.

However, the invention is not limited to forming plating layers 22 a onthe inner perimeters of the via holes 20 a, and the effects ofelectrical connection and heat release can both be obtained by havingthe paste bumps 50 a fill in the via holes 20 a.

The paste bump board is formed by printing and setting paste bumps 50 abeforehand on the copper foil 40 a, and then stacking the insulationmaterial 60 a such that the paste bumps 50 a penetrate the insulationmaterial 60 a to be exposed through the surface of the insulationmaterial 60 a. To this end, the paste bumps 50 a are formed such thatthe strength of the set paste bumps 50 a is greater than the strength ofthe insulation material 60 a.

Silver paste is typically used for the paste bumps 50 a, and the amountof a paste bump 50 a printed on the copper foil 40 a is determined incorrespondence with the size of the via hole 20 a formed in the coreboard 10 a. This is to allow the paste bumps 50 a to fill the via holes20 a when the paste bump boards are stacked onto the core board 10 a.

In stacking the paste bump boards on the core board 10 a such that thepaste bumps 50 a fill in the via holes 20 a, it is desirable that thestrength of the set paste bumps 50 a be lower than that of the coreboard 10 a. Thus, during the process of stacking the paste bump boardsonto the core board 10 a, the paste bumps 50 a are deformed according tothe shape of the via holes 20 a and are filled in the via holes 20 awithout causing damages to the core board 10 a.

After stacking the paste bump boards, outer layer circuits 42 a areformed on the copper foils 40 a of the paste bump boards, i.e. thesurfaces of the printed circuit board. As the paste bumps 50 a alsofunction as BVH's that electrically connect an inner layer circuit 30 aand an outer layer circuit 42 a, they are formed in a correspondingshape.

To readily and inexpensively manufacture a multilayer printed circuitboard through a collective stacking process by pressing on paste bumpboards, the paste bump boards are stacked on both surfaces of the coreboard 10 a. This is implemented by aligning the positions of the pastebumps with the positions of the via holes 20 a in the core board 10 aand then pressing on the paste bump boards.

FIG. 13 is a cross-sectional view of a printed circuit board using pastebumps according to another embodiment of the present invention. In FIG.13 are illustrated are illustrated a core board 10 a, copper foil layers12 a, via holes 20 a, plating layers 23a, inner layer circuits 30 a,copper foils 40 a, outer layer circuits 42 a, paste bumps 50 a, andinsulation materials 60 a.

As described earlier, plating layers 23 a are formed on the innerperimeters of the via holes 20 a in the core board 10 a for theinterlayer electrical connection between circuit patterns and forreleasing heat generated in the board, etc., while the remaining spacesare filled by the paste bumps 50 a.

In FIG. 13, the thickness of the plating layers 23 a formed on the innerperimeters of the via holes 20 a have been adjusted, unlike in FIG. 12,so that the paste bumps 50 a better fill the via holes 20 a. That is,the thickness of the plating layers 23 a is increased along a depth-wisedirection from the opening of the via holes 20 a, such that the shape ofthe via holes 20 a is in correspondence with the shape of the pastebumps 50 a.

For example, if the paste bumps 50 a are formed in a cone shape, thethickness of the plating layers 23 a is increased along the depth of thevia holes 20 a such that the via holes 20 a are formed in the shape of afunnel, in correspondence with the shape of the paste bumps 50 a,whereby the degree to which the paste bumps 50 a are deformed and filledin the via holes 20 a is improved.

If the paste bump boards are pressed onto both surfaces of the coreboard 10 a, as in embodiments of the present invention, increasing thethickness of the plating layers 23 a along a depth-wise direction fromthe openings, such that the interiors of the via holes 20 a have a shapesimilar to an hourglass, may improve the filling of the paste bumps 50a.

According to the present invention composed as set forth above, astructurally stable all-layer IVH structure can be implemented due toincreased strength in the BVH's of the plated core boards, themanufacture time can be reduced due to parallel processes and collectivestacking, implementing micro circuits can be made easy due to the copperfoils of the paste bump boards stacked on the outermost layers, themanufacture costs can be reduced as certain plating and drillingprocesses may be omitted, the interlayer connection area is increasedbetween circuit patterns for improved connection reliability, and dimplecoverage can be obtained.

Also, by using paste bumps to fill the via holes formed in the coreboards, the heat-releasing effect is improved, and as the interlayerelectrical connection paths between circuit patterns are made shorterdue to the implementation of an all-layer IVH stacking structure,induction noise is reduced.

In addition, since the multilayer printed circuit board is manufacturedby collectively stacking paste bump boards, the process is simplified,the lead time is decreased, and the manufacture cost is reduced, andsince the outer layer circuits are formed after stacking paste bumpboards each of which include a copper foil layer, the process of platingthe outer layers may be omitted, with a subtractive process applieddirectly on the copper foil layer to form more minute circuit patterns.

While the spirit of the invention has been described in detail withreference to particular embodiments, the embodiments are forillustrative purposes only and do not limit the invention. It is to beappreciated that those skilled in the art can change or modify theembodiments without departing from the scope and spirit of theinvention.

1. A method of manufacturing a printed circuit board using paste bumps,the method comprising: (a) perforating a core board to form at least onevia hole; (b) filling the at least one via hole by fill-plating andforming a circuit pattern on at least one surface of the core board; (c)stacking a paste bump board on at least one surface of the core board;and (d) forming an outer layer circuit on a surface of the paste bumpboard.
 2. The method of claim 1, wherein the core board is a copper cladlaminate.
 3. The method of claim 2, further comprising an operation ofremoving the copper foil layer in correspondence with a position wherethe at least one via hole is to be formed, before the operation (a) ofperforating a core board to form at least one via hole.
 4. The method ofclaim 2, further comprising an operation of reducing a thickness of thecopper foil layer by half-etching, between the operation (a) ofperforating a core board to form at least one via hole and the operation(b) of filling the at least one via hole by fill-plating and forming acircuit pattern on at least one surface of the core board.
 5. The methodof claim 1, wherein the at least one via hole is a blind via hole (BVH).6. The method of claim 1, wherein the paste bump board is formed by (e)printing at least one paste bump on a copper foil; (f) setting the atleast one paste bump; and (g) stacking an insulation material on thecopper foil such that the at least one paste bump penetrates theinsulation material.
 7. The method of claim 6, wherein a plating layerformed by the fill-plating in the at least one via hole comprises adimple, and the at least one paste bump is formed in correspondence witha position of the dimple.
 8. The method of claim 7, wherein the at leastone paste bump has a strength lower than that of the plating layer and astrength greater than that of the insulation material.
 9. The method ofclaim 6, wherein the at least one paste bump includes silver paste. 10.The method of claim 1, further comprising an operation of pressing thepaste bump board-onto the core board, between the operation (c) ofstacking a paste bump board on at least one surface of the core boardand the operation (d) of forming an outer layer circuit on a surface ofthe paste bump board.
 11. A method of manufacturing a printed circuitboard using paste bumps by collectively stacking at least one first coreboard, at least one second core board, and at least one outer layerboard, wherein the first core board is formed by: (a) forming at leastone BVH (blind via hole) on one surface of a core member; and (b)filling the at least one BVH by fill-plating and forming a circuitpattern on at least one surface of the core member, the second coreboard is formed by: (c) joining at least one core bump onto the othersurface of the core member of the first core board in a position wherethe at least one BVH is formed; (d) setting the at least one core bump;and (e) stacking a core insulation material on the other surface of thecore member such that the at least one core bump penetrates the coreinsulation material, and the outer layer board is formed by: (f) joiningat least one outer layer bump onto a copper foil; (g) setting the atleast one outer layer bump; and (h) stacking an outer layer insulationmaterial on the copper foil such that the at least one outer layer bumppenetrates the outer layer insulation material.
 12. The method of claim11, wherein the core member is a copper clad laminate (CCL).
 13. Themethod of claim 12, further comprising an operation of removing thecopper foil layer in correspondence with a position where the at leastone BVH is to be formed, before the operation (a) of forming at leastone BVH on one surface of a core member.
 14. The method of claim 12,further comprising an operation of reducing a thickness of the copperfoil layer by half-etching, between the operation (a) of forming atleast one BVH on one surface of a core member and the operation (b) offilling the at least one BVH by fill-plating and forming a circuitpattern on at least one surface of the core member.
 15. The method ofclaim 11, wherein the at least one core bump or the at least one outerlayer bump is formed by printing silver paste.
 16. The method of claim11, wherein a plating layer formed by the fill-plating in the at leastone BVH comprises a dimple, and the at least one core bump or the atleast one outer layer bump is formed in correspondence with a positionof the dimple.
 17. The method of claim 16, wherein the printed circuitboard is formed by aligning and stacking a plurality of the first coreboards or a plurality of the second core boards such that the at leastone core bump or the at least one outer layer bump is in correspondencewith a position of the dimple, and afterwards pressing the at least oneouter layer board on.
 18. A printed circuit board using paste bumps, theprinted circuit board comprising: a core board; a BVH (blind via hole)formed in the core board; a plating layer filled in the BVH; a circuitpattern formed on at least one surface of the core board; a dimpleincluded in the plating layer; and a paste bump board stacked on thecore board, wherein the paste bump board is formed by joining at leastone paste bump onto a copper foil and stacking an insulation material onthe copper foil such that the at least one paste bump penetrates theinsulation material.
 19. The printed circuit board of claim 18, whereinthe core board is a copper clad laminate (CCL).
 20. The printed circuitboard of claim 18, wherein the at least one paste bump is joined incorrespondence with a position of the dimple.
 21. The printed circuitboard of claim 20, wherein the at least one paste bump is filled in thedimple and electrically connected with the plating layer.
 22. Theprinted circuit board of claim 18, wherein the at least one paste bumphas a strength lower than that of the plating layer and a strengthgreater than that of the insulation material.
 23. The printed circuitboard of claim 18, further comprising an outer layer circuit formed byremoving portions of the copper foil.
 24. The printed circuit board ofclaim 18, further comprising an extra board positioned between the coreboard and the paste bump board, the extra board comprising: an extra BVH(blind via hole) formed on one surface of the extra board; an extraplating layer filled in the extra BVH; an extra circuit pattern formedon at least one surface of the extra board; an extra dimple included inthe extra plating layer; and an extra bump joined to the other side ofthe extra board in a position where the extra BVH is formed, wherein theextra bump is filled in the dimple and electrically connected with theplating layer, and the paste bump is filled in the extra dimple andelectrically connected with the extra plating layer.
 25. The printedcircuit board of claim 24, wherein the paste bump, the extra platinglayer, and the plating layer form an all-layer IVH (interstitial viahole).
 26. A method of manufacturing a printed circuit board using pastebumps, the method comprising: (a) perforating a core board to form atleast one via hole; (b) forming an inner layer circuit on at least onesurface of the core board; (c) stacking a paste bump board on at leastone surface of the core board; and (d) forming an outer layer circuit ona surface of the paste bump board.
 27. The method of claim 26, whereinthe core board is a copper clad laminate (CCL).
 28. The method of claim26, wherein the operation (a) of perforating a core board to form atleast one via hole comprises perforating the at least one via hole bymechanical drilling.
 29. The method of claim 26, wherein the operation(a) of perforating a core board to form at least one via hole furthercomprises forming a plating layer on an inner perimeter of the at leastone via hole.
 30. The method of claim 26, wherein the paste bump boardis formed by: (e) printing at least one paste bump on a copper foil incorrespondence with a position where the at least one via hole isformed; and (f) setting the at least one paste bump.
 31. The method ofclaim 30, further comprising an operation of stacking an insulationmaterial on the copper foil such that the at least one paste bumppenetrates the insulation material, after the operation (f) of settingthe at least one paste bump.
 32. The method of claim 30, wherein the atleast one paste bump includes silver paste.
 33. The method of claim 30,wherein an amount of the at least one paste bump is determined incorrespondence with a size of the at least one via hole such that the atleast one via hole is filled.
 34. The method of claim 30, wherein the atleast one paste bump has a strength lower than that of the plating layerand a strength greater than that of the insulation material.
 35. Themethod of claim 30, wherein the at least one paste bump is formed in ashape of a BVH (blind via hole) configured to electrically connect theinner layer circuit and the outer layer circuit.
 36. The method of claim26, wherein the operation (c) of stacking a paste bump board on at leastone surface of the core board comprises an operation of stacking thepaste bump board on both surfaces of the core board.
 37. The method ofclaim 36, further comprising an operation of pressing the paste bumpboard on both surfaces of the core board, between the operation (c) ofstacking a paste bump board on at least one surface of the core boardand the operation (d) of forming an outer layer circuit on a surface ofthe paste bump board.
 38. A printed circuit board using paste bumps, theprinted circuit board comprising: a core board; a via hole formed byperforating a portion of the core board; an inner layer circuit formedon at least one surface of the core board; a paste bump board, formed byjoining at least one paste bump onto a copper foil layer and stacking aninsulation material, and stacked on a surface of the core board; and anouter layer circuit formed on a surface of the paste bump board, whereinthe at least one paste bump is joined in correspondence with a positionof the via hole, and the via hole is filled by the at least one pastebump.
 39. The printed circuit board of claim 38, wherein the core boardis a copper clad laminate (CCL).
 40. The printed circuit board of claim38, wherein a plating layer is formed on an inner perimeter of the viahole.
 41. The printed circuit board of claim 40, wherein the platinglayer has varying thickness along its depth from an opening of the viahole such that the via hole is formed in a shape corresponding with ashape of the at least one paste bump.
 42. The printed circuit board ofclaim 40, wherein a thickness of the plating layer increases along itsdepth from an opening of the via hole.
 43. The printed circuit board ofclaim 38, wherein the paste bump board is formed by printing at leastone paste bump on a copper foil, setting the at least one paste bump,and afterwards stacking an insulation material on the copper foil suchthat the at least one paste bump penetrates the insulation material. 44.The printed circuit board of claim 38, wherein the at least one pastebump includes silver paste.
 45. The printed circuit board of claim 38,wherein an amount of the at least one paste bump is determined incorrespondence with a size of the via hole.
 46. The printed circuitboard of claim 38, wherein the at least one paste bump has a strengthlower than that of the plating layer and a strength greater than that ofthe insulation material.
 47. The printed circuit board of claim 38,wherein the at least one paste bump is formed in a shape of a BVH (blindvia hole) configured to electrically connect the inner layer circuit andthe outer layer circuit.
 48. The printed circuit board of claim 38,wherein the paste bump board is stacked on both surfaces of the coreboard.